The invention relates generally to photovoltaic devices and, in particular, to a method for producing photovoltaic devices which are substantially free of shorts and shunts.
Electrical shorts between the top and bottom conductive contacts of amorphous silicon p-i-n type solar cells frequently are formed during fabrication of the cells. Several methods have been suggested to prevent shorts in solar cells. Matsumara et al.; J. Appl. Phys. 61 1648 (1987) discloses a method to prevent short circuits. The disclosed method involves intermediates: i.e. glass substrates with a transparent conductive oxide (TCO) layer covered by an amorphous silicon layer. The amorphous silicon layer is intentionally fissured to confirm the usefulness of the method. The intermediate including the exposed transparent conductive oxide layer is placed in contact with an electrolyte solution of 0.5 mol/l of H.sub.2 SO.sub.4 including a platinum counter electrode and cathodically polarized at 0.7 volts relative to a saturated calomel electrode. As a result of such treatment, the transparent conductive oxide layer dissolves at pin holes. Subsequently, the amorphous silicon is coated with aluminum to produce a solar cell free from shorts.
The Izu, U.S. Pat. No. 4,451,970, discloses systems and methods for detecting and eliminating short circuit current paths through photovoltaic devices including at least one semiconductor region overlying a metallic substrate and a conductive light transmissive material overlying at least one semiconductor region. The elimination is provided by removing transparent conductive material from the pathway. As a result, the metal electrode and the TCO are electrically isolated.
The Murakami et al. U.S. Pat. No. 4,488,349, discloses a method of repairing shorts in parallel-connected vertical semiconductor devices by anodizing to form an insulating material in pin holes prior to formation of an electrode.
The Nostrand et al. U.S. Pat. No. 4,166,918, discloses a method of removing shorts by applying a reverse bias voltage to "burn out" the shorts. The applied voltage is less than the breakdown voltage of a solar cell.
The Hewig U.S. Pat. No. 4,544,797, discloses a method for preventing shorts and shunts by chemically etching at pinholes. The method passivates the unit prior to applying a second semiconductor layer. The passivation converts an exposed metal layer portion, associated with a pinhole, into an insulator.
The prior art also includes several teachings against applying a forward bias to semiconductor devices. Izu et al., in U.S. Pat. Nos. 4,510,674 and 4,510,675, teach the desirability of reverse bias over forward bias for detecting shorts in a solar cell. In foward bias, forward conduction is taught to decrease the ability to distinguish a shorted area from an acceptable area of a cell.
The Swartz, U.S. Pat. No. 4,385,971, also teaches that the rectifying junction of solar cells should be in reverse bias during any electrolytic etch in order to cause the electrical current to flow only through the short. Therefore, in order to etch a stainless steel/p-i-n/ITO structure according to Swartz, the stainless steel should be connected to a negative terminal of a DC source. 20% ammonium hydroxide is employed as an electrolyte. Swartz also teaches etching a stainless steel/N-I/platinum Schottky barrier type cell by connecting the stainless steel layer to the positive terminal of a DC source and immersing it in an electrolyte solution of dilute sulfuric or copper sulfate.